Highly-functional, multifunctional, and power saving electric devices have been developed for industrial use, for consumer use, and the like. With the development, CMOS circuits which operate at high speed with low power consumption are widely used in various fields. A CMOS circuit is composed of a P-channel insulated gate field effect transistor and an N-channel insulated gate field effect transistor. Transistor characteristics in an insulated gate field effect transistor including an MOS transistor or an MIS transistor are degraded due to bias temperature instability (“BTI”). In recent years, it has been revealed that the progress in miniaturization of insulated gate field effect transistors makes a Vth (threshold voltage) shift of the insulated gate field effect transistor due to the BTI larger than the conventional Vth shift. Especially, a Vth shift of a P-channel insulated gate field effect transistor due to negative bias temperature instability (“NBTI”) is more remarkable than a Vth shift of an N-channel insulated gate field effect transistor due to positive bias temperature instability (“PBTI”). Japanese Patent Application Publication No. 2006-252696 discloses a way to address the Vth shift.
A semiconductor integrated circuit having an insulated gate field effect transistor has a following problem. Specifically, if a certain voltage is applied to the logic gate, for example, for a long period, a P-channel insulated gate field effect transistor that constitutes a logic gate makes a larger Vth shift due to the NBTI at the time of a burn-in operation or at the stand-by than at the time of a normal operation. The increase in the Vth shift due to the NBTI causes degradation of operation margins of the logic gate and operation failure of the logic gate. Consequently, the Vth shift due to the NBTI leads to problems such as characteristic degradation and operation failure in a semiconductor integrated circuit including a logic gate or the like.